Instructor: Blaise Tine

Class location: PERLOFF 1102

Class time: T/R 4:00 PM - 5:45 PM

Instructor’s Office hours: Friday 4:30pm-5:30 Eng-VI 499.

TA: Turan Vural

TA’s office hours: will be posted at campuswire

Campuswire: https://campuswire.com/c/G259DFD21

Description

This course is designed to provide a foundational understanding of modern microprocessor architecture and how they execute application programs. We will delve into the fundamental concepts and strategies involved in computer design, including designing instruction set architectures (ISAs) and optimizing processor micro-architecture to improve instruction-level parallelism (ILP) and memory-level parallelism (MLP). We will cover topics such as pipelining, branch prediction, super-scalar architecture, out-of-order execution, cache prefetching, and power optimizations, among others.