Publications
You can also find my articles on my Google Scholar profile.
Conference & Journal Papers
VESICA: Fused Vector Extension for RISC-V Embedded GPUs
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026
PRISM: Accelerating Ray Tracing on RISC-V GPU
IEEE International Conference on Computer Design (ICCD), 2026
Inside VOLT: Designing an Open-Source GPU Compiler
ACM SIGPLAN International Conference on Compiler Construction (CC), 2026 · DOI
FastTrackGPU: Static-Analysis-Guided Analytical Modeling for Softcore GPUs
IEEE Computer Architecture Letters (CAL), 2026
Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2025 · DOI
SoftCUDA: Running CUDA on Softcore GPU
IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2025 · DOI
Towards “True” GPU Performance Scaling for OpenGPU
IEEE Hot Chips 36 Symposium (HCS), 2024 · DOI
Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs
28th Annual ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023 · DOI
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics
54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021 · DOI
Tango: an optimizing compiler for Just-In-Time RTL simulation
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020 · DOI
Pagevault: securing off-chip memory using page-based authentication
Proceedings of the International Symposium on Memory Systems (MEMSYS), 2017 · DOI
Workshop Papers
TinyVortex: Learning-Guided Kernel Scheduling for Configurable SIMT GPU Co-Design Space Exploration
Workshop on Learning-Augmented Compilers & Systems (LACS), co-located with PACT 2026, 2026 · Code
Thread-Scalable 2:4 Structured Sparsity on an Open RISC-V GPU
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
RTL Design and Analysis of Sparse Tensor Cores for Unstructured Sparsity in RISC-V GPUs
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
Multiport Support for Vortex OpenGPU Memory Hierarchy
1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC), co-located with DATE 2025, 2025 · PDF
Implementing Hardware Extensions for Multicore RISC-V GPUs
6th Workshop on Computer Architecture Research with RISC-V (CARRV), 2022
The Tip of Iceberg in Open-Source Hardware GPU
Workshop on Open-Source Computer Architecture Research (OSCAR), 2022
Bringing OpenCL to Commodity RISC-V CPUs
5th Workshop on Computer Architecture Research with RISC-V (CARRV), 2021 · PDF
Supporting CUDA for an extended RISC-V GPU architecture
5th Workshop on Computer Architecture Research with RISC-V (CARRV), 2021 · PDF
Cryptography Acceleration in a RISC-V GPGPU
5th Workshop on Computer Architecture Research with RISC-V (CARRV), 2021 · PDF
Cash: a single-source hardware-software codesign framework for rapid prototyping
Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), 2021
Posters
Supporting Async Barrier and TMA for Vortex GPGPU (POSTER)
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
PRISM: Accelerating Ray Tracing on RISC-V GPU (POSTER)
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
Hardware Acceleration of GPU Kernel Scheduling on RISC-V GPU (POSTER)
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
gem5-Vortex: Heterogeneous Cross-ISA Integration of a RISC-V GPGPU in gem5 (POSTER)
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
CycleFence: Precise Cycle-Level Profiling for RISC-V GPUs (POSTER)
Workshop on Open-Source Computer Architecture Research (OSCAR), 2026
Accelerating Graphic Rendering on Programmable RISC-V GPUs (POSTER)
IEEE Hot Chips 34 Symposium (HCS), 2022 · PDF
A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs (POSTER)
58th Design Automation Conference (DAC), Designer Track, 2021
Vortex: A Reconfigurable RISC-V GPGPU Accelerator for Architecture Research (POSTER)
IEEE Hot Chips 32 Symposium (HCS), 2020 · PDF
Productive Hardware Designs using Hybrid HLS-RTL Development (POSTER)
International Symposium on Field-Programmable Gate Arrays (FPGA), 2020 · DOI
Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping (POSTER)
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2020 · DOI
Tango: An Optimizing Compiler for Just-In-Time RTL Simulation (POSTER)
28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2019 · DOI
Preprints
Vortex: OpenCL Compatible RISC-V GPGPU
arXiv preprint arXiv:2002.12151, 2020 · PDF
Patents
Rasterization of compute shaders
A Glaister, BP Tine, D Sessions, M Lyapunov, Y Dotsenko
US Patent 9,529,575
Vectorization of shaders
A Glaister, BP Tine, B Pelton, D Sessions, M Lyapunov, Y Dotsenko
US Patent 8,806,458
Scalar optimizations for shaders
A Glaister, BP Tine, D Sessions, M Lyapunov, Y Dotsenko
US Patent 9,430,199
Lookup tables for text rendering
BP Tine, CN Raubacher, AJR Hodsdon, MM Cohen
US Patent 9,129,441