Blaise-Pascal Tine

Blaise-Pascal Tine

Assistant Professor of Computer Science, UCLA · ORCAS Lab

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Pages

About Me

Assistant Professor of Computer Science at UCLA and director of the ORCAS lab.

pensees

The Day My Plane Crashed

7 minute read

Published:

I was born in Cameroon, in West Africa, where the sky in the dry season looks impossibly high and blue. Sometimes an airplane would cross that sky: tiny, silver, and loud. I would stop whatever I was doing and stare. How did it stay up there? What kept it from falling?

The Tree of Life

17 minute read

Published:

Part 1: The Secret Hiding in Plain Sight

The Walking Doll

15 minute read

Published:

Part 1: The Doll with a Heartbeat

projects

publications

Pagevault: securing off-chip memory using page-based authentication

Authors: Blaise-Pascal Tine, Sudhakar Yalamanchili

Published in Proceedings of the International Symposium on Memory Systems (MEMSYS), 2017

Recommended citation: Blaise-Pascal Tine and Sudhakar Yalamanchili. 2017. Pagevault: securing off-chip memory using page-based authentication. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Association for Computing Machinery, New York, NY, USA, 293–304. https://doi.org/10.1145/3132402.3132439

Tango: An Optimizing Compiler for Just-In-Time RTL Simulation (POSTER)

Authors: Blaise Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter

Published in 28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2019

Recommended citation: Blaise Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter. Tango: An Optimizing Compiler for Just-In-Time RTL Simulation (POSTER). In Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques (PACT 2019), pp. 480-481. https://doi.org/10.1109/PACT.2019.00055

Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping (POSTER)

Authors: Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeff Vetter, Hyesoon Kim

Published in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2020

Recommended citation: Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeff Vetter, Hyesoon Kim. Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping (POSTER). In Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '20), p. 321. https://doi.org/10.1145/3373087.3375340

Productive Hardware Designs using Hybrid HLS-RTL Development (POSTER)

Authors: Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim

Published in International Symposium on Field-Programmable Gate Arrays (FPGA), 2020

Recommended citation: Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim. Productive Hardware Designs using Hybrid HLS-RTL Development (POSTER). In Proceedings of the International Symposium on Field-Programmable Gate Arrays

Vortex: OpenCL Compatible RISC-V GPGPU

Authors: Fares Elsabbagh, Blaise Tine, Priyadarshini Roshan, Ethan Lyons, Euna Kim, Da Eun Shim, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim

Published in arXiv preprint arXiv:2002.12151, 2020

Recommended citation: Fares Elsabbagh, Blaise Tine, Priyadarshini Roshan, Ethan Lyons, Euna Kim, Da Eun Shim, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim. Vortex: OpenCL Compatible RISC-V GPGPU. arXiv preprint arXiv:2002.12151, 2020. https://arxiv.org/abs/2002.12151

Tango: an optimizing compiler for Just-In-Time RTL simulation

Authors: Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim

Published in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020

Recommended citation: Blaise Tine, Sudhakar Yalamanchili, and Hyesoon Kim, 'Tango: An Optimizing Compiler for Just-In-Time RTL Simulation,' in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, pp. 157-162, doi: 10.23919/DATE48585.2020.9116253.

Vortex: A Reconfigurable RISC-V GPGPU Accelerator for Architecture Research (POSTER)

Authors: Fares Elsabbagh, Blaise Tine, Apurve Chawda, Will Gulian, Yaotian Feng, Priyadarshini Roshan, Ethan Lyons, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim

Published in IEEE Hot Chips 32 Symposium (HCS), 2020

Recommended citation: Fares Elsabbagh, Blaise Tine, Apurve Chawda, Will Gulian, Yaotian Feng, Priyadarshini Roshan, Ethan Lyons, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim. Vortex: A Reconfigurable RISC-V GPGPU Accelerator for Architecture Research (POSTER). In Proceedings of the 2020 IEEE Hot Chips 32 Symposium (HCS) https://vortex.cc.gatech.edu/publications/hotchips-poster.pdf

Cash: a single-source hardware-software codesign framework for rapid prototyping

Authors: Blaise Tine, Sudhakar Yalamanchili, Hyesoon Kim

Published in Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), 2021

Recommended citation: Blaise Tine, Sudhakar Yalamanchili, Hyesoon Kim. Cash: a single-source hardware-software codesign framework for rapid prototyping. In Proceedings of the 2021 Workshop on Languages, Tools, and Techniques for Accelerator Design

Supporting CUDA for an extended RISC-V GPU architecture

Authors: Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim

Published in 5th Workshop on Computer Architecture Research with RISC-V (CARRV), 2021

Recommended citation: Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim. Supporting CUDA for an extended RISC-V GPU architecture. In Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV 2021). https://carrv.github.io/2021/papers/CARRV2021_paper_66_Han.pdf

Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics

Authors: Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Hyesoon Kim

Published in 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021

Recommended citation: Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, and Hyesoon Kim, 'Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics,' in MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '21). Association for Computing Machinery, New York, NY, USA, 754–766. https://doi.org/10.1145/3466752.3480128

A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs (POSTER)

Authors: Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Sung Kyu Lim, Hyesoon Kim

Published in 58th Design Automation Conference (DAC), Designer Track, 2021

Recommended citation: Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Sung Kyu Lim, Hyesoon Kim. A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs (POSTER). 58th Design Automation Conference (DAC), Designer Track, 2021.

The Tip of Iceberg in Open-Source Hardware GPU

Authors: Blaise Tine, Ruobing Han, Hyesoon Kim

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2022

Recommended citation: Blaise Tine, Ruobing Han, Hyesoon Kim. The Tip of Iceberg in Open-Source Hardware GPU. In Proceedings of the Workshop on Open-Source Computer Architecture Research (OSCAR 2022).

Implementing Hardware Extensions for Multicore RISC-V GPUs

Authors: Blaise Tine, Hyesoon Kim

Published in 6th Workshop on Computer Architecture Research with RISC-V (CARRV), 2022

Recommended citation: Blaise Tine, Hyesoon Kim. Implementing Hardware Extensions for Multicore RISC-V GPUs. In Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV 2022).

Accelerating Graphic Rendering on Programmable RISC-V GPUs (POSTER)

Authors: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim

Published in IEEE Hot Chips 34 Symposium (HCS), 2022

Recommended citation: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim. Accelerating Graphic Rendering on Programmable RISC-V GPUs (POSTER). In Proceedings of the 2022 IEEE Hot Chips 34 Symposium (HCS) https://hc34.hotchips.org/assets/program/posters/HC2022.vortex.BlaiseTine.v01.pdf

Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs

Authors: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim

Published in 28th Annual ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023

Recommended citation: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim. Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs. In Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems.

Towards “True” GPU Performance Scaling for OpenGPU

Authors: Blaise Tine, Hyesoon Kim

Published in IEEE Hot Chips 36 Symposium (HCS), 2024

Recommended citation: Blaise Tine, Hyesoon Kim. Towards “True” GPU Performance Scaling for OpenGPU. IEEE Hot Chips 36 Symposium (HCS), 2024. https://doi.org/10.1109/HCS61935.2024.10665202

Multiport Support for Vortex OpenGPU Memory Hierarchy

Authors: Injae Shin, Blaise Tine

Published in 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC), co-located with DATE 2025, 2025

Recommended citation: Injae Shin, Blaise Tine. Multiport Support for Vortex OpenGPU Memory Hierarchy. 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC), co-located with DATE 2025, 2025. arXiv:2503.17602. https://arxiv.org/abs/2503.17602

SoftCUDA: Running CUDA on Softcore GPU

Authors: Chihyo Ahn, Ruobing Han, Udit Subramanya, Jisheng Zhao, Blaise Tine, Hyesoon Kim

Published in IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2025

Recommended citation: Chihyo Ahn, Ruobing Han, Udit Subramanya, Jisheng Zhao, Blaise Tine, Hyesoon Kim. SoftCUDA: Running CUDA on Softcore GPU. IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2025. https://doi.org/10.1109/FCCM62733.2025.00049

Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels

Authors: Martin Troiber, Martin Schulz, Blaise Tine, Hyesoon Kim

Published in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2025

Recommended citation: Martin Troiber, Martin Schulz, Blaise Tine, Hyesoon Kim. Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2025. https://doi.org/10.1109/ISPASS64960.2025.00053

FastTrackGPU: Static-Analysis-Guided Analytical Modeling for Softcore GPUs

Authors: Chihyo Ahn, Shinnung Jeong, Liam Paul Cooper, Ruobing Han, Huanzhi Pu, Nicholas Parnenzini, Jisheng Zhao, Blaise Tine, Hyesoon Kim

Published in IEEE Computer Architecture Letters (CAL), 2026

Recommended citation: Chihyo Ahn, Shinnung Jeong, Liam Paul Cooper, Ruobing Han, Huanzhi Pu, Nicholas Parnenzini, Jisheng Zhao, Blaise Tine, Hyesoon Kim. FastTrackGPU: Static-Analysis-Guided Analytical Modeling for Softcore GPUs. IEEE Computer Architecture Letters (CAL), vol. 25, no. 1, pp. 162-165, 2026.

Inside VOLT: Designing an Open-Source GPU Compiler

Authors: Shinnung Jeong, Chihyo Ahn, Huanzhi Pu, Jisheng Zhao, Hyesoon Kim, Blaise Tine

Published in ACM SIGPLAN International Conference on Compiler Construction (CC), 2026

Recommended citation: Shinnung Jeong, Chihyo Ahn, Huanzhi Pu, Jisheng Zhao, Hyesoon Kim, Blaise Tine. Inside VOLT: Designing an Open-Source GPU Compiler. ACM SIGPLAN International Conference on Compiler Construction (CC), 2026, pp. 155-167. https://doi.org/10.1145/3771775.3786275

CycleFence: Precise Cycle-Level Profiling for RISC-V GPUs (POSTER)

Authors: Xinle Song, Blaise Tine

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2026

Recommended citation: Xinle Song, Blaise Tine. CycleFence: Precise Cycle-Level Profiling for RISC-V GPUs (POSTER). Workshop on Open-Source Computer Architecture Research (OSCAR), 2026.

Hardware Acceleration of GPU Kernel Scheduling on RISC-V GPU (POSTER)

Authors: Randall Liu, Blaise Tine

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2026

Recommended citation: Randall Liu, Blaise Tine. Hardware Acceleration of GPU Kernel Scheduling on RISC-V GPU (POSTER). Workshop on Open-Source Computer Architecture Research (OSCAR), 2026.

PRISM: Accelerating Ray Tracing on RISC-V GPU (POSTER)

Authors: Kuan Fu Chen, Blaise Tine

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2026

Recommended citation: Kuan Fu Chen, Blaise Tine. PRISM: Accelerating Ray Tracing on RISC-V GPU (POSTER). Workshop on Open-Source Computer Architecture Research (OSCAR), 2026.

RTL Design and Analysis of Sparse Tensor Cores for Unstructured Sparsity in RISC-V GPUs

Authors: Georgios Triantafyllou, Panagiotis-Eleftherios Eleftherakis, Konstantinos Iliakis, Blaise Tine, Sotirios Xydis

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2026

Recommended citation: Georgios Triantafyllou, Panagiotis-Eleftherios Eleftherakis, Konstantinos Iliakis, Blaise Tine, Sotirios Xydis. RTL Design and Analysis of Sparse Tensor Cores for Unstructured Sparsity in RISC-V GPUs. Workshop on Open-Source Computer Architecture Research (OSCAR), 2026.

Thread-Scalable 2:4 Structured Sparsity on an Open RISC-V GPU

Authors: Yanggon Kim, Xinle Song, Blaise Tine

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2026

Recommended citation: Yanggon Kim, Xinle Song, Blaise Tine. Thread-Scalable 2:4 Structured Sparsity on an Open RISC-V GPU. Workshop on Open-Source Computer Architecture Research (OSCAR), 2026.

Supporting Async Barrier and TMA for Vortex GPGPU (POSTER)

Authors: Chengxuan Wang, Blaise Tine

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2026

Recommended citation: Chengxuan Wang, Blaise Tine. Supporting Async Barrier and TMA for Vortex GPGPU (POSTER). Workshop on Open-Source Computer Architecture Research (OSCAR), 2026.

PRISM: Accelerating Ray Tracing on RISC-V GPU

Authors: Kuan Fu Chen, Blaise Tine

Published in IEEE International Conference on Computer Design (ICCD), 2026

Recommended citation: Kuan Fu Chen, Blaise Tine. PRISM: Accelerating Ray Tracing on RISC-V GPU. IEEE International Conference on Computer Design (ICCD), 2026.

VESICA: Fused Vector Extension for RISC-V Embedded GPUs

Authors: Dao Xian Ding, Michael Srouji, Brandon Kam, Nader Sehatbakhsh, Blaise Tine

Published in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026

Recommended citation: Dao Xian Ding, Michael Srouji, Brandon Kam, Nader Sehatbakhsh, Blaise Tine. VESICA: Fused Vector Extension for RISC-V Embedded GPUs. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026.

talks

teaching

ECE8823 - GPU Architectures

Graduate course, Georgia Institute of Technology, 2018

Lead teaching assistant, with several guest lectures. The course covers the basic principles of parallel programming using CUDA and OpenCL, and introduces students to advanced microarchitecture concepts unique to single-instruction multiple-thread (SIMT) processors.

CS3220 - Processor Design

Intermediate-level Course, Georgia Institute of Technology, 2022

It is a project-driven course teaching the principles of hardware design tailored towards modern CPU and GPU implementations. The course also introduces students to the RISC-V ISA and FPGA development, with practical lab experiments to learn about Verilog RTL design and high-level synthesis.

CS3220 - Processor Design

Intermediate-level Course, Georgia Institute of Technology, 2023

It is a project-driven course teaching the principles of hardware design tailored towards modern CPU and GPU implementations. The course also introduces students to the RISC-V ISA and FPGA development, with practical lab experiments to learn about Verilog RTL design and high-level synthesis.

CS 254A - Advanced GPU Microarchitecture

Graduate course, University of California, Los Angeles, 2025

Taught in the fall quarter. The course takes students to the research frontier of GPU design, including modern tensor-core architecture: the Tensor Memory Accelerator (TMA), structured sparsity, and warp-group matrix-multiply-accumulate (WGMMA) instructions. Students study these features on a full tensor-GPU stack built on Vortex, which they can read, modify, and measure end to end.

CS M151B - Computer Systems Architecture

Undergraduate course, University of California, Los Angeles, 2026

Taught in the winter quarter. The course covers the fundamentals of computer architecture, from instruction sets and pipelining to memory hierarchies.