Blaise-Pascal Tine

Blaise-Pascal Tine

Assistant Professor

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A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.

Pages

Posts

Future Blog Post

less than 1 minute read

Published:

This post will show up by default. To disable scheduling of future posts, edit config.yml and set future: false.

Blog Post number 4

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 3

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 2

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 1

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

portfolio

projects

publications

Pagevault: securing off-chip memory using page-based authentication

Authors: Blaise-Pascal Tine, Sudhakar Yalamanchili

Published in Proceedings of the International Symposium on Memory Systems (MEMSYS), 2017

Recommended citation: Blaise-Pascal Tine and Sudhakar Yalamanchili. 2017. Pagevault: securing off-chip memory using page-based authentication. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Association for Computing Machinery, New York, NY, USA, 293–304. https://doi.org/10.1145/3132402.3132439

Productive Hardware Designs using Hybrid HLS-RTL Development (POSTER)

Authors: Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim

Published in International Symposium on Field-Programmable Gate Arrays (FPGA), 2020

Recommended citation: Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim. Productive Hardware Designs using Hybrid HLS-RTL Development (POSTER). In Proceedings of the International Symposium on Field-Programmable Gate Arrays

Tango: an optimizing compiler for Just-In-Time RTL simulation

Authors: Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim

Published in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020

Recommended citation: Blaise Tine, Sudhakar Yalamanchili, and Hyesoon Kim, 'Tango: An Optimizing Compiler for Just-In-Time RTL Simulation,' in 2020 Design, Automation & Test in Europe Conference & Exhiition (DATE), 2020, pp. 157-162, doi: 10.23919/DATE48585.2020.9116253.

Cash: a single-source hardware-software codesign framework for rapid prototyping

Authors: Blaise Tine, Sudhakar Yalamanchili, Hyesoon Kim

Published in Workshop on Languages, Tools, and Techniques for Accelerator Design (LATE), 2021

Recommended citation: Blaise Tine, Sudhakar Yalamanchili, Hyesoon Kim. Cash: a single-source hardware-software codesign framework for rapid prototyping. In Proceedings of the 2021 Workshop on Languages, Tools, and Techniques for Accelerator Design

Vortex: A Reconfigurable RISC-V GPGPU Accelerator for Architecture Research (POSTER)

Authors: Fares Elsabbagh, Blaise Tine, Apurve Chawda, Will Gulian, Yaotian Feng, Priyadarshini Roshan, Ethan Lyons, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim

Published in IEEE Hot Chips 32 Symposium (HCS), 2021

Recommended citation: Fares Elsabbagh, Blaise Tine, Apurve Chawda, Will Gulian, Yaotian Feng, Priyadarshini Roshan, Ethan Lyons, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim. Vortex: A Reconfigurable RISC-V GPGPU Accelerator for Architecture Research (POSTER). In Proceedings of the 2020 IEEE Hot Chips 32 Symposium (HCS)

An Optimizing Compiler for Just-In-Time RTL Simulation (POSTER)

Authors: Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter

Published in International Conference on Parallel Architectures and Compilation Techniques (PACT), 2021

Recommended citation: Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter. An Optimizing Compiler for Just-In-Time RTL Simulation (POSTER). In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques

Supporting CUDA for an extended RISC-V GPU architecture

Authors: Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim

Published in 4th Workshop on Computer Architecture Research with RISC-V (CARRV), 2021

Recommended citation: Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim. Supporting CUDA for an extended RISC-V GPU architecture. In Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV 2021).

Bringing OpenCL to Commodity RISC-V CPUs

Authors: Tine Blaise, Seyong Lee, Jeff Vetter, Hyesoon Kim

Published in 4th Workshop on Computer Architecture Research with RISC-V (CARRV), 2021

Recommended citation: Tine Blaise, Seyong Lee, Jeff Vetter, Hyesoon Kim. Bringing OpenCL to Commodity RISC-V CPUs. In Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV 2021).

Cryptography Acceleration in a RISC-V GPGPU

Authors: Austin Adams, Pulkit Gupta, Blaise Tine, Hyesoon Kim

Published in 5th Workshop on Computer Architecture Research with RISC-V (CARRV), 2021

Recommended citation: Austin Adams, Pulkit Gupta, Blaise Tine, Hyesoon Kim. Cryptography Acceleration in a RISC-V GPGPU. In Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV 2021).

Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics

Authors: Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Kim Hyesoon

Published in 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021

Recommended citation: Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, and Kim Hyesoon, 'Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics,' in MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '21). Association for Computing Machinery, New York, NY, USA, 754–766. https://doi.org/10.1145/3466752.3480128

The Tip of Iceberg in Open-Source Hardware GPU

Authors: Blaise Tine, Ruobing Han and Hyesoon Kim.

Published in Workshop on Open-Source Computer Architecture Research (OSCAR), 2022

Recommended citation: Blaise Tine, Ruobing Han and Hyesoon Kim. The Tip of Iceberg in Open-Source Hardware GPU. In Proceedings of the Workshop on Open-Source Computer Architecture Research (OSCAR 2022).

Implementing Hardware Extensions for Multicore RISC-V GPUs

Authors: Tine Blaise, Hyesoon Kim

Published in 6th Workshop on Computer Architecture Research with RISC-V (CARRV), 2022

Recommended citation: Tine Blaise, Hyesoon Kim. Implementing Hardware Extensions for Multicore RISC-V GPUs. In Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV 2022).

Accelerating Graphic Rendering on Programmable RISC-V GPUs (POSTER)

Authors: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim

Published in IEEE Hot Chips 34 Symposium (HCS), 2022

Recommended citation: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim. Accelerating Graphic Rendering on Programmable RISC-V GPUs (POSTER). In Proceedings of the 2022 IEEE Hot Chips 34 Symposium (HCS)

Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs

Authors: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim

Published in 28th Annual ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023

Recommended citation: Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim. Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs. In Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems.

talks

teaching

ECE8823 - GPU Architectures

Graduate course, Georgia Institute of Technology, 2018

Lead teaching assistant with several guest lectures. The courses covers the basic principles of parallel programming using CUDA and OpenCL, and introduces students to advanced microarchitecture concepts unique to single-instruction-multiple-threads (SIMT) processors.

CS3220 - Processor Design

Intermediate-level Course, Georgia Institute of Technology, 2022

It is project-driven course teaching the principles of hardware design tailored towards modern CPU and GPU implementations. The course also introduces students to the RISC-V ISA and FPGAs development, with practical lab experiments to learn about Verilog RTL design and high-level synthesis.

CS3220 - Processor Design

Intermediate-level Course, Georgia Institute of Technology, 2023

It is project-driven course teaching the principles of hardware design tailored towards modern CPU and GPU implementations. The course also introduces students to the RISC-V ISA and FPGAs development, with practical lab experiments to learn about Verilog RTL design and high-level synthesis.